For NAND flash memory devices, both the physical scaling and the electrical scaling have become more challenging with each technology node.
In state-of-the-art NAND flash memory devices, the oxide-nitride-oxide (ONO) interpoly dielectric (IPD), which can more generally be referred to as the gate dielectric, runs along the sidewalls of the floating gate in order to provide a large capacitance between floating gate and control gate and, in turn, a large coupling ratio. As the IPD layer is present twice in one width defined by the pitch, scaling of the thickness of the IPD layer in a floating gate flash device becomes a limiting factor for flash scaling below a 2× generation technology node, which corresponds to a memory cell half-pitch between 20 nm and 29 nm inclusive. To achieve good data retention, the physical thickness of the IPD layer is limited to about 12 to 15 nm using state-of-the art materials, which corresponds to a minimum pitch size of about 24 to 30 nm, as it is still necessary to add the thickness of the floating gate and the control gate.
FIG. 1 shows a schematic representation of a typical floating gate memory device on a substrate 1, comprising floating gate structures 2, isolation areas 3, interpoly dielectric layer 4 wrapped around the floating gate structures 2, tunnel oxide layers 5 and a control gate 6. It is seen that the scaling of the pitch P of the floating gate memory device becomes a great challenge as it is necessary within the pitch P to have room for the floating gate structures (FGSs) 2, for an interpoly dielectric (IPD) layer 4, for a control gate (CG) 6 and for another interpoly dielectric (IPD) layer 4. With the materials currently used for the IPD layer (e.g., ONO or aluminum oxide-based (AlO-based) dielectric stack, the thickness of the IPD layer is limited to about 12 to 15 nm in order to achieve good data retention (e.g., about 10 years of data retention) for the floating gate memory device. When scaling to smaller thickness, the electrical properties of the materials currently used for the IPD layer are no longer sufficient, as the smaller thickness causes increased leakage and bad performance of the device.